According to an EETimes article worldwide sales of semiconductor equipment rose 148% over 2009. This represents a strong rebound from the global recession. The breakdown is given in the table below from SEMI.
2009-2010 Semiconductor Capital Equipment Market by World Region
(Dollar in U.S. billions; Percentage Year-over-Year)
Region 2009 2010 % Change China 0.94 3.63 286% Europe 0.97 2.33 142% Japan 2.23 4.44 99% South Korea 2.60 8.33 220% North America 3.39 5.76 70% Taiwan 4.35 11.19 157% Rest of World 1.44 3.85 168% Total 15.92 39.54 148% Source: SEMI/SEAJ March 2011
Rest of World wraps locations including Singapore and Malaysia
China has overtaken Europe in equipment spending and North American share of equipment spending fell from 21% in 2009 to 15% in 2010, an indication of further decline in US semiconductor manufacturing. In fact North American spending increased at slower rate than any other region.
I have just installed Mathematica 8.0.1. No changes are immediately evident with the exception of a plugin for the new computable data format (CDF). I do wish Wolfram Research would publish release notes with these minor releases. It is really difficult to find out what changes have been made. I have been tracking two bugs with their new CUDA functions that I reported to Wolfram shortly after the release of 8.0.0. I am happy to report that CUDAFourier now works on 2D arrays larger than 724X724 on my Nvidia GTX 570 card — before I would get an error on any array 725X725 or larger. (I will run some benchmarks on the larger arrays when I have the time.) So that is clearly one improvement. Unfortunately another issue has not been fixed. I discovered a memory leak error that shows up when CUDAMemoryLoad/CUDAMemoryUnload is used with single precision numbers. This shows up in the task manager as an irreversible memory consumption. I am sorry to say that I have no idea what else has or has not been fixed. Any comments from others would be welcome.
Wolfram Research is apparently rolling out a minor release 8.0.1 to its existing customers. Stay tuned for what improvements are in this release.
Dr. Dobbs has a review of Mathematica 8 up. Here are the top twenty new features from that review:
- C code generation and compilation to a dynamic library or standalone executable
- Dynamic libraries linking into Mathematica at run-time (no need to restart the Mathematica 8 environment)
- Native support for Compute Unified Device Architecture (CUDA) and OpenCL GPU parallelization
- Free-form Linguistic Input
- Wolfram|Alpha integration
- Improved Graphic Rendering
- Expanded Image and Video Processing
- Text Recognition in Images
- Oscillatory integration
- Permutation Group calculations
- New statistical functions like Non-Parametric Distributions, tool-tip data visualizations
- Financial Engineering functions that span massive number of types of trading indicators, symbolic representation of cash flows, effective intreats rates, annuities, etc. and a comprehensive FinancialDerivative super-function, an InteractiveTradingChart function, and more
- Expanded image processing, including morphology, segmentation and feature detection
- Arbitrary geometric transformations and image alignment
- Bode, Nyquist, and Nichols control system visualization plots
- Discrete and continuous wavelet transform analysis (for example, DiscreteWaveletTransform, WavletImagePlot functions) that follow the standard conventions of the field
- Expanded network analysis (Data and Social network data analysis)
- Various graphs: export to GraphML, GXL and other popular formats
Evidently semiconductor capital expensitures are expected to reach a new record high of $47.2 B according to this EE Times article.
“Total spending on fab projects could approach $47.2 billion this year, above the estimated $38.6 billion spent in 2010,” said Christian Gregor Dieseldorff, senior analyst at SEMI, in a statement. “2011 spending will finally exceed the peak year’s 2007 fab spending of $46.4 billion.”
Some companies have increased their capital spending. For example, Taiwan Semiconductor Manufacturing Co. Ltd. increased its capital spending from a record $5.9 billion in 2010 to another record high of $7.8 billion in 2011. Intel Corp. increased capital spending from $5.2 billion in 2010 to $9.0 billion in 2011. Globalfoundries Inc. doubled its 2010 capex from $2.7 billion to $5.4 billion in 2011.
The optical lithography sessions of the conference were dominated by two topics: double patterning and free form source mask optimization (SMO). Double patterning encompasses several techniques to evade optical resolution limitations. One uses a single exposure to build two lines by depositing material on both sides of a single lithographically defined line by various deposition and etch processes. Another is two split the pattern into two or more masking steps and construct the desired resist pattern with two or more exposures. It turns out the decomposition of the patterns is not a trivial problem. Free form SMO is a technique whereby the source is divided into many pixels that are turned on in patterns that are determined by computer simulation optimizations that simultaneously construct a mask pattern. The optimized source and mask deliver an exposed pattern that is closest to what is desired. This process is computationally expensive and is often done only on selected clips of the full chip that contain the most challenging patterns to print. then the problem becomes one of constructing a strategy that selects the clips. These techniques will be used at the 22 nm node and below with state of the art immersion 193 nm scanners; of course, if EUV is ready many of these complexities can be avoided.
While listening to presentations concerning the development of EUV lithography I began to reflect on the similarities between this technology and the supersonic transport (SST) in aviation. The SST was next in the logical evolution of aviation from balloons to dirigibles to bi-planes and triplanes to faster propeller mono-wings to the first subsonic passenger jets. Every development strove for increased speed just as lithography has striven for increased resolution. And in fact the SST did achieve its speed potential just as EUV is showing record resolution results. A limited number of SSTs (primarily the Concord but also the Tupolev) were placed into commercial use. From Wikipedia:
Concorde
Main article: Concorde aircraft historiesIn total, 20 Concordes were built, six for development and 14 for commercial service.
These were:
- Two prototypes
- Two pre-production aircraft
- 16 production aircraft
- The first two of these did not enter commercial service
- Of the 14 that flew commercially, 8 were still in service in April 2003
All but two of these aircraft, a remarkably high percentage for any commercial fleet, are preserved; the two that are not preserved are F-BVFD (cn 211), parked as a spare-parts source in 1982 and scrapped in 1994, and F-BTSC (cn 203), which crashed in Paris on July 25, 2000.
[edit] Tupolev 144
A total of 16 airworthy Tu-144s were built: the prototype Tu-144 reg 68001, a pre-production Tu-144S reg 77101, nine production Tu-144S reg 77102 – 110, and five Tu-144D reg 77111 – 115. A seventeenth Tu-144 (reg 77116) was never completed. There was also at least one ground test airframe for static testing in parallel with the prototype 68001 development.
And it turns out the Concord was commercially profitable. Also form Wikipedia:
Concorde only sold to British Airways and Air France, with subsidized purchases that were to return 80% of the profits to the government. In practice for almost all of the length of the arrangement, there was no profit to be shared. After Concorde was privatised, cost reduction measures (notably the closing of the metallurgical wing testing site which had done enough temperature cycles to validate the aircraft through to 2010) and ticket price raises led to substantial profits.
Since Concorde stopped flying it has been revealed that over the life of Concorde, the plane did prove profitable, at least to British Airways. Concorde operating costs over nearly 28 years of operation were approximately £1 billion, with revenues of £1.75 billion.[6]
But in the end the SST could not compete with the slower but more fuel efficient passenger jet for the commercial airline business. One possible fate for EUV is to be successful in only a narrow range of applications that can afford the increased cost while the mainstream IC industry competes on low cost, low power, and 3D packaging technologies. The industry has already invested $1 B in the technology so it is already in the same ballpark as SST development costs. Like the SST, its true fate will probably only become clear after a few systems are put into commercial use. Time will tell.
Shiang-Yi Chiang, Senior VP R&D, gave the TSMC plenary talk. This was a much more nuts and bolts talk than the IMEC presentation and focused on TSMC’s plans for future device nodes. He stated that TSMC had specific cost targets for moving to the next device node — otherwise it would not be attractive to their end customers. Wafer costs can go up but must provide increased value from number of devices per area and performance. 50% of the allowable cost increase is allocated to lithography. TSMC appears to be hedging their litho bets: they are strong e-beam direct write supporters (especially Burn Lin) however they are taking delivery of an EUV scanner in mid 2011. They already have an e-beam Mapper system in house undergoing testing. Dr. Chiang stated that they would need an increase of 20X in EUV source power to attain cost targets for high volume manufacturing.
He spent part of his talk advocating for 450 mm wafers. At one point he showed a graph of the cost ratio between generation n and generation n-1 through the nodes. There was an inflection point at the 28nm/40nm point where costs were increasing rapidly – hence the need to move to 450 mm to bring the costs down. He expected a 30% cost reduction for the devices from this change and made the argument that the move would save manpower, resources, and land. He even said they had a problem supplying enough engineers for expansions. TSMC plans were to target 450 mm at the 20 nm node in pilot line mode in 2013/2014 and at the 14 nm node in volume production in 2015/2016. In the Q&A session, in response to a question of how to get the equipment suppliers on board, he said their were fewer equipment suppliers around now than there were when changing to 300 mm wafer sizes so competition was not as big a spur and that they were considering a semiconductor manufacturer/government consortium to fund 50% of the cost of wafer equipment development. One comment he added was that the expected equipment R&D cost was $1.5 billion and this cost over three years was only something like 10% of the aggregate equipment suppliers R&D budget.
Finally, one interesting technology he spent some time on was the use of a Si interposer to reduce size and improve performance. This is a layer of fine pitch interconnect on a silicon substrate between multiple device die and the underlying PC board. The ratio of PC board minimum pitch to Si interconnect pitch is something like 10,000 so large gains in interconnect area can be saved.
Luc Van den Hove gave a great overview of the future of electronics applications and the device and lithographic technologies that would be required to achieve them. The first part included some compelling but strangely disturbing animated videos of the projected use of electronics in the future. These included smart bio-sensor patches that would communicate wirelessly in real time. Maybe I’m having a Ted Kaczynski moment but I kept thinking of the commercial and governmental opportunities for abuse when every aspect of our lives is connected to the global network.
As far as lithography goes, Luc claimed that the EUV tool had acheived a 20X increase in throughput from improvement in laser power and only another factor of 10 was required for volume manufacturing. Not much to ask for when each tool will go for from somewhere between $50 and $100 million dollars.
Not being satisfied with the performance of the GTX 460 Nvidia card described in a recent post I have acquired a GTX 570 video card. The two simple benchmarks I have been easily able to do are a repeated matrix multiply and a FFT using the Mathematica CUDA commands. The results are shown in the table below. The GTX 570 has 480 cores as opposed to the GTX 460′s 288 cores and the matrix multiply performance scales pretty closely to the ratio of the core number. I don’t trust the FFT results because there is obviously something awry with the algorithm.
Unfortunately, I have confirmed two CUDA Mathematica bugs with their tech support. The CUDAFourier command does not appear to work for matrices larger than about 600 x 600 on either the GTX 460 or the GTX 570 – it does on some of the older cards it was tested on however. Also there is a bug with the CUDAMemoryLoad function for single precision computations. Presumably both will be fixed eventually. In the meantime perhaps I can devise a more thorough test using CUDAFunctionLoad, but that will take more work.
